1. Field of the Invention
The present invention relates to the formation of a shallow trench isolation structure in semiconductor wafer fabrication. More particularly, the present invention relates to the formation of a shallow trench isolation structure with reduced trench parasitic capacitance.
2. Description of the Related Art
Semiconductor wafer fabrication involves a series of processes used to create semiconductor devices and integrated circuits (ICs) in and on a semiconductor wafer surface. Fabrication typically involves the basic operations of layering and patterning, together with others such as doping, and heat treatments. Layering is an operation used to add thin layers of material (typically insulator, semi-conductor or conductor) to the surface of the semiconductor wafer. Layers are typically either grown (for example, thermal oxidation of silicon to grow a silicon dioxide dielectric layer) or deposited by a variety of techniques such as chemical vapor deposition (CVD) and physical vapor deposition (PVD), including evaporation and sputtering. Patterning, is an operation that is used to remove specific portions of the top layer or layers on the wafer surface. Patterning is usually accomplished through the use of photolithography (also known as photomasking) to transfer the semiconductor design to the wafer surface.
Patterning is often used to expose an area to be etched, such as to create a trench for creation of an isolation structure. More particularly, isolation structures are often created, for instance, to separate different devices from one another.
Semiconductor device sizes have decreased dramatically over the years. In order to accommodate sub-micron IC feature sizes, various technologies have been developed and applied. Since IC feature sizes are small, shallow junctions are used, for example, to create source and drain regions. Also, shallow trench isolation has becomes preferred over LOCOS.
A conventional Shallow Trench Isolation (STI) scheme is illustrated in FIG. 1. As shown, at first, a protective blanket pad oxide 102 is grown over the silicon substrate 104, followed by a blanket nitride 106 deposition. The nitride 106 is then patterned, for example, using a photoresist and anti-reflective coating layer. Subsequently, the open areas are etched to create one or more trenches 108. Etching is typically performed with a highly anisotropic plasma. The photoresist is then stripped and thin oxide 110 (e.g., silicon dioxide) is grown, lining the exposed trench. This liner 110 helps remove any etch-related damage. Subsequently, an oxide film 112 is deposited in the trench, completely filling the trench areas 108 up to and above the nitride surface 106. The wafer is then planarized, using methods like Chemical Mechanical Planarization, resulting in the deposited insulator filling up only the trench areas. Current trench fill processes use standard silicon oxide (e.g., SiO2) type materials, which typically have a dielectric constant of between approximately 3.9 and 4.2. For instance, the dielectric constant of silicon dioxide is 3.9. High density plasma CVD (HDP-CVD), tetraethoxysilane-Ozone CVD (TEOS-Ozone CVID), Plasma Enhanced-CVD (PE-CVD) or Flow-Fill processes are commonly used. The results are void free, oxide filled isolation. Depending upon the quality of the deposited oxide, an additional densification step, either in oxygen or in a neutral atmosphere may be performed to improve its quality. The liner oxidation 110 detailed earlier can also be bundled into the step of depositing the oxide film 112 in the trench. Chemical Mechanical Polishing (CMP) is then typically performed to planarize the topology of the wafer surface.
As described above, current technology trends are forcing isolation regions to smaller spacing. For example, for devices with 0.1 micron nodes, isolation spacing has been projected to be in the order of about 0.13 microns. Shrinking horizontal dimensions may also lead to shrinking of trench depth (i.e., vertical dimensions) of the isolation structure as well due at least in part to tool limitations in filling high aspect ratio trenches. Capacitance is proportional to the dielectric constant and inversely proportional to the separation distance between two conductors. Thus, the reduction in feature sizes leads to an undesirable increase in trench parasitic capacitance.
The various components of capacitance associated with a trench isolation dielectric are illustrated in FIG. 2. More specifically, capacitances are shown in relation to trench (isolation) height 202. As shown, a horizontal trench parasitic capacitor 204 is shown in relation to trench width 206. In addition, depletion capacitor 208 and the corresponding depletion width 210 are also shown. Moreover, the contribution of a trench to junction capacitance 212 is also illustrated. A vertical trench parasitic capacitor 214 is shown, which varies with the trench height 202. Thus, this figure illustrates the various components of capacitance, including horizontal and vertical trench capacitances that will increase as technology advances enable trench dimensions to decrease.
In view of the above, what are needed are methods and compositions for defining an isolation structure with a low isolation parasitic capacitance.